These days, the importance of a flash memory is increased due to remarkable development of portable multimedia devices. Of these, a NAND flash memory not only has a storage device of a high capacity but also is relatively low in price compared to other memories, and so it is suitable for a portable storage device.
On the other hand, the NAND flash memory does not support a random access which is supported by memory devices such as SRAM, DRAM, FRAM, MRAM, and PRAM, should perform a data read operation in a page unit and should perform a data write operation after erasing previous data. For these reasons, it takes a long time to write data, and an actual use of the NAND flash memory requires a lot of complementation in a software side due to a limitation to the number of data write times.
For example, data should be stored according to a certain rule in order to store and read data in a computing device, and what names a file, locates a position (directory) of a file and expresses information related to security and authority logically and physically is called a file system.
A file system designed to read and write data in a file unit for a characteristic of the NAND flash memory is a Yet Another Flash Filing System (YAFFS) which is a log-structured file system which automatically provides a wear leveling function and the strength for the power interruption.
Here, a flash memory has a limited life span that data can be recorded in each sector, and the wear leveling function is a softwarical method which prevents an electrical erasing operation for repetitively being performed for a certain sector so that an electric erasing operation can be uniformly performed for all sectors and so all sectors can be evenly used, thereby leveling a life span of all sectors.
FIG. 1 is a block diagram illustrating a conventional flash memory device having a file system mounted therein. As shown in FIG. 1, a NAND flash memory 10 and a DRAM 20 are provided. The NAND flash memory 10 comprises a plurality of page data cells 12 and a plurality of spare data cells 14.
In FIG. 1, the NAND flash memory 10 has a plurality of pages which are formed such that object headers comprised of a plurality of page data stored in a plurality of page data cells 12 match with a plurality of tags stored in a plurality of spare data cells 14 by one-to-one correspondence.
The NAND flash memory 10 stores page data such as the size of data and a file to be written from an external portion and information as to whether data are read or written in a plurality of page data cells 12 and stores spare data such as a boot loader, an error correcting code (ECC), information about a bad block, and information about the number of deletion times in a plurality of spare data cells 14. This is because the NAND flash memory 10 allows weak cells more or less and so an additional storage space for storing these information are needed.
The DRAM 20 receives information which are stored by scanning the object header data stored in a plurality of page data cells 12 and the tag data in a plurality of spare data cells and performs an address-mapping operation for them in a tree structure when the file system is mounted in the flash memory device attached to a portable multimedia device.
However, since the flash memory device can not support a random access, in order to boot the flash memory device mounted onto the system, relevant data are first copied to the DRAM 20 which supports a random access, and then a central processing unit (CPU) accesses the DRAM 20 to perform a program.
At this time, a mounting time is very long since the DRAM 20 scans data in the NAND flash memory 10 to select a file, and a data erase operation should be performed in advance before recording data in order to record data, and a softwarical complementation such as a wear leveling for levelly recording data in the whole flash memory is needed due to a garbage collection for reducing a recording time and a limitation to the number of recording times.
Here, the garbage collection is a task for gathering garbage areas of a storage device so that a program can use them, and the garbage area is an area which is actually not being used and can not be used by another program since a user program asks a storage device to use a certain area necessary for an operating system but does not return the area even after finishing a use of the area.
FIG. 2 is a block diagram illustrating a booting operation of a NAND chip which improves reading and writing speeds of the conventional flash memory device. As shown in FIG. 2, a NAND flash memory 10, an SRAM 30, and a control logic portion 40, a memory controller 70 are provided. The NAND flash memory 10 comprises a plurality of page data cells and a plurality of spare data cells.
Functions of the components which perform a booting operation of the NAND chip are described below with reference to FIG. 2.
The NAND flash memory 10 stores page data such as the size of data and a file to be written from an external portion and information as to whether data are read or written in a plurality of page data cells and stores spare data such as a boot loader, an ECC, information about a bad block, and information about the number of deletion times in a plurality of spare data cells.
The SRAM 30 receives the booting code dumped from the boot loader stored in a plurality of spare data cells of the NAND flash memory 10 to store the information while serving as a data write and read buffer.
The control logic portion 40 comprises a register, an ECC circuit, and an address generating circuit. The control logic portion 40 stores an address and a command provided outside the chip, corrects a one-bit error when data are transferred to the SRAM 30 from the NAND flash memory 10, and receives an initial address of data to be read and then automatically generates addresses and store them in the SRAM 30 again.
The memory controller 70 receives the booting code which is dumped to and temporarily stored in the SRAM 30 to boot a corresponding operating system of an electronic device system by using a predetermined booting program and provides address information containing an initial address of read data and a command to the control logic portion 40. That is, the memory controller 70 overally controls an operation of the NAND chip.
A file system mounting and booting operation of the NAND chip is described below with reference to FIGS. 1 and 2.
For better understanding, let us assume that an operating system specific to an electron device system such as a portable computer (PC) or a portable multimedia device is booted after the flash memory device is attached to the electronic device system and then the file system is mounted onto the flash memory device.
The NAND flash memory 10 stores page data such as the size of data and a file to be written from an external portion and information as to whether data are read or written in a plurality of page data cells and stores spare data such as a boot loader, an ECC, information about a bad block, and information about the number of deletion times in a plurality of spare data cells.
The DRAM 20 receives information which are stored by scanning the object header data stored in a plurality of page data cells and the tag data in a plurality of spare data cells and performs an address-mapping operation for them in a tree structure when the file system of the flash memory device is mounted.
The SRAM 30 receives the booting code dumped from the boot loader stored in a plurality of spare data cells of the NAND flash memory 10 to temporarily store the information, and the control logic portion 40 stores an address and a command provided from the memory controller 70, receives an initial address of data to be read, and then automatically generates addresses and store them in the SRAM 30 again.
The memory controller 70 receives the booting code which is dumped to and temporarily stored in the SRAM 30 to boot a corresponding operating system of the electronic device system by using a predetermined booting program.
Meanwhile, the flash memory has a limited life span that data can be recorded in each sector, the life span closely relates to the number of times of electrical erase performed for each sector, and if the number of electrical erase times exceeds a predetermined value, there may occur an error in recording data.
In order to extend the life span of the flash memory, the number of erase times of the NAND flash memory 10 and a block setting of the NAND flash memory 10 to be deleted are controlled. The conventional NAND chip separately needs areas in the NAND flash memory 10 for a plurality of spare data cells which store a boot loader, an ECC, information about a bad block, and information about the number of deletion times and also needs a process for temporarily storing information such as the ECC, the information about the bad block and information about the number of deletion times in the DRAM 20 and a process for dumping the booting code stored in a plurality of spare data cells from the boot loader to the SRAM 30 when the electronic device system is booted.
For these reasons, a speed for writing/reading data onto/from the NAND flash memory 10 is slow, and there is a problem in that data may be lost when powered off because the SRAM 30 temporarily store data as the data write and read buffer.
FIG. 3 is a block diagram illustrating a flash memory system with a conventional NAND flash memory. The flash memory system of FIG. 3 comprises a latching and decoding portion 15, a control logic 25, a NAND flash memory cell array 35, a NAND flash page buffer 45, a NAND flash column selecting portion 55, a buffer portion 65, an SRAM 75, a memory bus 60, a memory controller 70, and a CPU 80. The NAND flash memory cell array 35 is divided into a plurality of pages which comprise a plurality of page data cells and a plurality of spare data cells, each page comprises one or more sectors, and each sector comprises a plurality of memory cells.
An operation of the conventional NAND flash memory system is described below with reference to FIG. 3.
When address information ADD and a command COM are applied from the electronic device system, the latching and decoding portion 15 latches, decodes and stores the information. The address information ADD contains a row address, a column address, a sector address, information about the number of sectors, and a page address. The command COM contains read and write commands, a program command, and an erase command.
The control logic 25 overally controls an operation of the flash memory device according to which command the command COM stored in the latching and decoding portion 15 represents, and controls the NAND flash page buffer portion 45 according to the sector address and the information about of the number of sectors provided from the latching and decoding portion 15. For example, in case of desiring to read data corresponding to one sector in the NAND flash memory cell array 35, the control logic 25 controls the NAND flash page buffer portion 45 so that only the page buffers belonging to the selected sector can perform the read operation.
The NAND flash page buffer portion 45 comprises a plurality of page buffers which respectively correspond to columns of the NAND flash memory cell array 35, and reads data from the NAND flash memory cell array 35 under control of the control logic 60 during the read operation and temporarily stores the read data. The data may contain spare data as well as page data.
In response to a control operation of the control logic 25, the NAND flash column selecting portion 55 sequentially selects the page buffers of the NAND flash page buffer portion 45 in a certain unit according to the column address information ADD from the latching and decoding portion 15 and then outputs data bits of the selected page buffers.
The buffer portion 65 temporarily stores the data bits transmitted through the NAND flash column selecting portion 55 and outputs stored data DO under control of the control logic 25 when data of one page stored in the NAND flash page buffer portion 45 are inputted.
As the data write and read buffer, the SRAM 75 receives data through the memory bus and transfers the data to the buffer portion 65 when the write command is applied or receives page data stored in the page data cells in the NAND flash memory cell array 35 and outputs the page data outside the memory system while receiving the boot code which is stored in the spare data cells and dumped from the boot loader and temporarily storing the information.
The memory controller 70 provides the address information and the command to the flash memory device through the memory bus 60 and overally controls an operation of the flash memory device.
The CPU 80 executes an internal booting program to boot a corresponding operating system of the electronic device system by using the booting code which is copied to the SRAM which supports a random access since the flash memory device can not support a random access.
As described above, in the conventional NAND flash memory device and the flash memory system, a plurality of spare data cells are located in the same row as a plurality of page data cells so that all of a plurality of page data cell areas and all of a plurality of spare data cell areas are selected by one row address, and they operates by distinguishing page data and spare data by using the column address.
When a defective block is found by testing the NAND flash memory 10, an operation for setting it as a defective block through defective block information of a plurality of spare data cells is performed, and there is a problem in that the erasing and writing speed is slow since a plurality of spare data cell areas comprise the NAND flash memory cell.